The present invention relates to an OTP (One Time Programmable) memory.
To store confidential information (for example, key information for encryption of an STB (Set Top Box)), an OTP memory is used. In such an OTP memory, as described in patent literatures 1 to 3, an anti-fuse of a gate oxide film breakdown type is used to record data.
As a reference technique, FIG. 1 shows an example of a cross section of an OTP memory. One memory cell isolated by a device isolation region 102 is drawn. An NMOS transistor (selection transistor 110) is coupled to an NMOS gate capacitance (fuse 111) via a diffusion layer. A thin gate oxide film 108 (having a thickness of, for example, less than 5 nm) is formed for the fuse 111 and a thick gate oxide film 107 (having a thickness of, for example, over 5 nm) is formed for the selection transistor.
By applying high voltage Vpp (≧gate oxide film breakdown voltage, for example, 7V) to a fuse gate 106, voltage Vdd_high (≧Vdd, for example, 2.5V) to a selection transistor gate 105, and 0V to a diffusion layer 103 on the selection transistor side, the gate oxide film 108 of the fuse is broken and information is written. At the time of reading the information, Vdd (for example, 1.5V) is applied to the fuse gate 106 (the others are similar to the above). Current is passed to a cell in which the gate oxide film is broken and no current is passed to a cell in which the gate oxide film is not broken, thereby reading information.
FIG. 2 shows an array configuration of the OTP memory and voltage relations at the time of writing. Information is written in a cell C11 since the potential of the fuse gate 106 is Vpp and the potential of the selection transistor gate 105 is Vdd_high. Information cannot be written in a cell C21 for a reason that Vpp is not applied to the fuse gate 106. In a cell C12, the potential of the selection transistor gate 105 is 0V and breakdown current does not sufficiently flow via the selection transistor 110, so that the gate oxide film is not broken. Information cannot be written in a cell C22 for a reason that both of the potential of the fuse gate 106 and the potential of the selection transistor gate 105 are 0V. Therefore, information can be selectively written only in desired cells.
FIG. 3 shows voltage relations at the time of reading. The relations are similar to those at the time of writing except that the potential of the fuse gate 106 is Vdd, and data in desired cells can be selectively read.